Invention Grant
- Patent Title: Branch prediction power reduction
- Patent Title (中): 分支预测功率降低
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Application No.: US13458513Application Date: 2012-04-27
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Publication No.: US09547358B2Publication Date: 2017-01-17
- Inventor: Aneesh Aggarwal , Ross Segelken , Paul Wasson
- Applicant: Aneesh Aggarwal , Ross Segelken , Paul Wasson
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F1/32

Abstract:
In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.
Public/Granted literature
- US20130290676A1 BRANCH PREDICTION POWER REDUCTION Public/Granted day:2013-10-31
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