Invention Grant
- Patent Title: System and method for discovering unknown problematic patterns in chip design layout for semiconductor manufacturing
- Patent Title (中): 用于发现半导体制造芯片设计布局中未知问题模式的系统和方法
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Application No.: US14810428Application Date: 2015-07-27
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Publication No.: US09547745B1Publication Date: 2017-01-17
- Inventor: Shauh-Teh Juang , Jason Zse-Cherng Lin
- Applicant: DMO Systems Limited
- Applicant Address: TW ZhuBei
- Assignee: DMO Systems Limited
- Current Assignee: DMO Systems Limited
- Current Assignee Address: TW ZhuBei
- Agency: Lin & Associates Intellectual Property, Inc.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system includes a critical signature library for storing critical signature databases of chip design layouts in semiconductor manufacturing and a statistical model creator for creating statistical models based on the known problematic circuit patterns stored in the critical signature databases and a target specification based on deviation between physical measurement and simulation data or design data associated with the known problematic circuit patterns. The system further has a statistical model based predictor for predicting and discovering unknown problematic circuit patterns by applying the statistical models to a large number of candidate circuit patterns generated from a random layout generator, or extracted from the chip design layout based on hot spot sites determined by extended lithographic process check on the chip design layout or inspecting wafers manufactured with the chip design layout with an aggressive sensitivity setting.
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