Invention Grant
- Patent Title: Integrated circuit stack including a patterned array of electrically conductive pillars
- Patent Title (中): 集成电路堆叠，包括导电柱的图案化阵列
-
Application No.: US14692154Application Date: 2015-04-21
-
Publication No.: US09548277B2Publication Date: 2017-01-17
- Inventor: Eric E. Vogt , Gregor D. Dougal , James L. Tucker
- Applicant: Honeywell International Inc.
- Applicant Address: US NJ Morris Plains
- Assignee: Honeywell International Inc.
- Current Assignee: Honeywell International Inc.
- Current Assignee Address: US NJ Morris Plains
- Agency: Shumaker & Sieffert, P.A.
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L23/28 ; H01L21/56 ; H01L25/00 ; H01L23/498
Abstract:
The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.
Public/Granted literature
- US20160315055A1 INTEGRATED CIRCUIT STACK INCLUDING A PATTERNED ARRAY OF ELECTRICALLY CONDUCTIVE PILLARS Public/Granted day:2016-10-27
Information query
IPC分类:
