Invention Grant
- Patent Title: Methods and apparatus for passive equalization in high-speed and high density integrated circuits
- Patent Title (中): 高速和高密度集成电路无源均衡的方法和装置
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Application No.: US14980894Application Date: 2015-12-28
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Publication No.: US09548278B1Publication Date: 2017-01-17
- Inventor: Jian Liu , Hui Liu
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01P3/08 ; H01P11/00 ; H01L23/66
Abstract:
A passive equalization structure is provided. The passive equalization structure includes a semiconductor substrate having first and a differential pair having first and second signal conductors. The first signal conductor is formed in a first layer of the semiconductor substrate. The second signal conductor is formed in a second layer in the semiconductor substrate that is different than the first layer. The passive equalization structure further includes first and second reference planes, whereby the first and second signal conductors are formed between the first and second reference planes. The first reference plane has a first thickness, and the first signal conductor has a second thickness that is different than the first thickness. A conductive via may short the first and second reference to minimize uncertainty and variations in capacitance from the first and second signal conductors and unwanted stray capacitance effects.
Information query
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