Invention Grant
US09548317B2 FDSOI semiconductor structure and method for manufacturing the same
有权
FDSOI半导体结构及其制造方法
- Patent Title: FDSOI semiconductor structure and method for manufacturing the same
- Patent Title (中): FDSOI半导体结构及其制造方法
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Application No.: US14397586Application Date: 2012-05-22
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Publication No.: US09548317B2Publication Date: 2017-01-17
- Inventor: Haizhou Yin , Huilong Zhu , Zhijiong Luo
- Applicant: Haizhou Yin , Huilong Zhu , Zhijiong Luo
- Applicant Address: CN Beijing
- Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee Address: CN Beijing
- Agency: Osha Liang LLP
- Priority: CN201210134597 20120428
- International Application: PCT/CN2012/075913 WO 20120522
- International Announcement: WO2013/159416 WO 20131031
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L27/12 ; H01L29/66 ; H01L29/786 ; H01L21/02 ; H01L21/266 ; H01L21/306 ; H01L21/308 ; H01L21/768 ; H01L29/78 ; H01L21/74 ; H01L21/265 ; H01L29/165

Abstract:
The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which then connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which then saves device area and simplifies manufacturing process accordingly.
Public/Granted literature
- US20150145046A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2015-05-28
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