Test circuitry for an integrated circuit (IC) that has a scan chain includes a control unit for applying a test pattern and a clock signal to the scan chain, and for varying the level of a supply voltage during a scan test procedure. In a first test phase, the supply voltage is set to the rated voltage level of the IC while a test pattern is shifted into the scan chain at a fast rate. A second, capture phase is run at a lower rate and the supply voltage is reduced to a lower level such that defects that cannot be detected when the capture phase is run at the rated voltage are observable yet switching elements in the IC still function correctly. Running the shift phase at the higher speed reduces the overall test time compared with known very low voltage (VLV) scan test procedures.