Invention Grant
- Patent Title: Block partition to minimize power leakage
- Patent Title (中): 块分区,以最大限度地减少功率泄漏
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Application No.: US14278566Application Date: 2014-05-15
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Publication No.: US09552051B2Publication Date: 2017-01-24
- Inventor: Vinu K. Elias , Sridharan Ranganathan , Paul S. Durley
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: International IP Law Group, P.L.L.C.
- Main IPC: G06F1/32
- IPC: G06F1/32 ; H03K3/01

Abstract:
Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal Serial Bus (USB) physical subsystem and system firmware, wherein the system firmware conveys USB related events to the SOC. The system is configured to include a power management apparatus, where the power management apparatus includes USB wake functionality and USB On-the-Go (OTG) functionality.
Public/Granted literature
- US20150333735A1 BLOCK PARTITION TO MINIMIZE POWER LEAKAGE Public/Granted day:2015-11-19
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