Invention Grant
- Patent Title: Probabilistic flit error checking
- Patent Title (中): 概率飞行错误检查
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Application No.: US14495797Application Date: 2014-09-24
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Publication No.: US09552253B2Publication Date: 2017-01-24
- Inventor: Venkatraman Iyer , Robert G. Blankenship , Debendra Das Sharma
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; H04L1/00 ; G06F13/42

Abstract:
A bit error in a flit transmitted over a link is determined to affect one or more particular bits of the flit based on a syndrome value associated with a cyclic redundancy check (CRC) value of the flit. The link includes a plurality of lanes. It is determined that the one or more particular bits were sent over one or more particular lanes of the link. The bit error is associated with the one or more particular lanes based on determining that the affected bits were transmitted over the particular lanes.
Public/Granted literature
- US20160085619A1 PROBABILISTIC FLIT ERROR CHECKING Public/Granted day:2016-03-24
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