Invention Grant
- Patent Title: Test logic for a serial interconnect
- Patent Title (中): 串行互连的测试逻辑
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Application No.: US14581000Application Date: 2014-12-23
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Publication No.: US09552269B2Publication Date: 2017-01-24
- Inventor: Debendra Das Sharma , Daniel S. Froelich
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: International IP Group, P.L.L.C.
- Main IPC: G06F11/263
- IPC: G06F11/263 ; G06F11/22 ; G06F13/42 ; G06F13/40 ; G06F13/00 ; H04L1/00 ; H03M13/09

Abstract:
An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages, wherein each reporting message is associated with a link sub-segment in a link in the serial interconnect, and each reporting message comprises a status region for the associated link sub-segment to report transmission errors. The test logic also includes analysis logic to record errors in the link sub-segment.
Public/Granted literature
- US20160179647A1 TEST LOGIC FOR A SERIAL INTERCONNECT Public/Granted day:2016-06-23
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