Invention Grant
US09552454B2 Concurrent timing-driven topology construction and buffering for VLSI routing
有权
并行时序驱动拓扑结构和缓冲用于VLSI路由
- Patent Title: Concurrent timing-driven topology construction and buffering for VLSI routing
- Patent Title (中): 并行时序驱动拓扑结构和缓冲用于VLSI路由
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Application No.: US14603696Application Date: 2015-01-23
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Publication No.: US09552454B2Publication Date: 2017-01-24
- Inventor: Salim Chowdhury , Akshay Sharma
- Applicant: Oracle International Corporation
- Applicant Address: US CA Redwood City
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: US CA Redwood City
- Agency: Brooks Kushman P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and method for topology construction for long and complex fan-out networks such as encountered in microprocessors include a modified Steiner tree algorithm with concurrent buffering to reduce post-buffer power/delay cost for a spanning tree. The system and method may prune Hanan points prior to calling a buffering tool to insert buffers and insert non-Hanan branching points. Embodiments may also include dividing a device into a plurality of super unit blocks, performing routing within each of the plurality of super units using a single crossing Steiner tree algorithm to determine a corresponding port, and aligning corresponding ports of each super unit to provide routing between the plurality of super units.
Public/Granted literature
- US20150213188A1 CONCURRENT TIMING-DRIVEN TOPOLOGY CONSTRUCTION AND BUFFERING FOR VLSI ROUTING Public/Granted day:2015-07-30
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