An image processing apparatus includes a plurality of image processing module parts, a module arbiter part, and a DMAC (Direct Memory Access Controller) part. Each of the image processing module parts includes a module core for executing a predetermined image processing. The plurality of image processing module parts is connected to the module arbiter part. The module arbiter part arbitrates memory access which is given by the plurality of image processing module parts through a bus. The DMAC part is connected between the module arbiter part and the bus, and executes memory access related to the arbitration result obtained by the module arbiter part.