An address generation circuit includes: a first address control clock generation unit suitable for generating a first address control clock signal in response to an internal clock signal; a second address control clock generation unit suitable for generating a second address control clock signal in response to one of an address initialization signal and the first address control clock signal; an address counting unit suitable for counting the second address control clock signal and generating a counting address; and a repair control unit suitable for latching the counting address in response to the second address control clock signal, comparing the latched counting address with a repair address, and generating a redundancy address based on the comparison result.