A memory device including first to fourth cell blocks, each including a plurality of normal columns and one or more redundancy columns and a control unit suitable for repairing the normal columns using the redundancy columns in the first and the second cell blocks using first repair information and repairing the normal columns using the redundancy columns in the third and the fourth cell blocks using second repair information when the memory device is set as a first mode, and suitable for repairing the normal columns using the redundancy columns in the first and the third cell blocks using the first repair information and repairing the normal columns using the redundancy columns in the second and the fourth cell blocks using the second repair information when the memory device is set as a second mode.