Embodiments herein describe DRAM that includes storage circuitry coupled between complementary bit lines which are in turn coupled to the same sense amplifier. The storage circuitry includes a transistor and a storage capacitor coupled in series. The gate of the transistor is coupled to a word line which selectively couples the storage capacitor to one of the complementary bit lines. Because the capacitor is coupled to both of the bit lines, when reading the data stored on the capacitor, the charge on the capacitor causes current to flow from one of the bit lines into the other bit line which causes a voltage difference between the complementary bit lines. Put differently, both ends of the capacitor are electrically coupled to bit lines thereby generating a larger voltage difference between the bit lines when reading data from the storage capacitors.