A semiconductor memory device includes a plurality of memory cells connected to a plurality of word lines; a peripheral circuit suitable for applying a program pulse to at least one of the word lines, performing a program verification operation to the plurality of memory cells by using a first program verification voltage; and a control logic suitable for controlling the peripheral circuit to repeat the applying of the program pulse and the performing the program verification operation until program verification passes by increasing a level of the program pulse by an amount of a step voltage at each repetition, wherein a size of the step voltage decreases at each repetition.