Invention Grant
- Patent Title: Methods of forming reduced resistance local interconnect structures and the resulting devices
- Patent Title (中): 形成降低的电阻局部互连结构和所得器件的方法
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Application No.: US14219365Application Date: 2014-03-19
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Publication No.: US09553028B2Publication Date: 2017-01-24
- Inventor: Ruilong Xie , Ryan Ryoung-Han Kim
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L29/66 ; H01L23/485 ; H01L21/768 ; H01L23/532

Abstract:
A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.
Public/Granted literature
- US20150270176A1 METHODS OF FORMING REDUCED RESISTANCE LOCAL INTERCONNECT STRUCTURES AND THE RESULTING DEVICES Public/Granted day:2015-09-24
Information query
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