Invention Grant
- Patent Title: Edge termination for trench gate FET
- Patent Title (中): 沟槽栅极FET的边缘端接
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Application No.: US14473358Application Date: 2014-08-29
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Publication No.: US09553184B2Publication Date: 2017-01-24
- Inventor: Moaniss Zitouni , Edouard de Frésart , Pon Sung Ku , Ganming Qin
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L21/265 ; H01L21/768 ; H01L29/423
Abstract:
A semiconductor device includes a semiconductor layer disposed at a substrate and a plurality of active cells disposed at the semiconductor layer. Each active cell includes a trench extending into the semiconductor layer and a body region disposed in the semiconductor layer adjacent to a sidewall of the trench and at a first depth below the surface of the semiconductor layer. The semiconductor device further includes a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells. The termination cell includes a trench extending into the semiconductor layer, and further includes a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second depth less than the first depth. The body regions of the active cells and of the termination cell have a conductivity type different than that of the semiconductor layer.
Public/Granted literature
- US20160064546A1 EDGE TERMINATION FOR TRENCH GATE FET Public/Granted day:2016-03-03
Information query
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