Invention Grant
- Patent Title: FET device having a vertical channel in a 2D material layer
- Patent Title (中): FET器件在2D材料层中具有垂直沟道
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Application No.: US14586725Application Date: 2014-12-30
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Publication No.: US09553199B2Publication Date: 2017-01-24
- Inventor: Tuo-Hung Hou , Samuel C. Pan
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. , National Chiao Tung University
- Applicant Address: TW Hsin-Chu TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.,National Chiao Tung University
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.,National Chiao Tung University
- Current Assignee Address: TW Hsin-Chu TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/417 ; H01L29/423 ; H01L29/10 ; H01L21/762 ; H01L21/768 ; H01L29/66
Abstract:
Semiconductor devices and methods of forming the same are provided. A source/drain electrode stack is formed over a substrate, wherein the source/drain electrode stack comprises a first source/drain electrode and a second source/drain electrode. A source/channel/drain layer is formed on a sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material. A gate stack is formed on the source/channel/drain layer.
Public/Granted literature
- US20160190343A1 A FET DEVICE HAVING A VERTICAL CHANNEL IN A 2D MATERIAL LAYER Public/Granted day:2016-06-30
Information query
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