Invention Grant
- Patent Title: Dimension calculation method for a semiconductor device
- Patent Title (中): 半导体器件的尺寸计算方法
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Application No.: US14175278Application Date: 2014-02-07
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Publication No.: US09558565B2Publication Date: 2017-01-31
- Inventor: Sajal Biring
- Applicant: MATERIALS ANALYSIS TECHNOLOGY INC
- Applicant Address: TW Hsinchu
- Assignee: MATERIALS ANALYSIS TECHNOLOGY INC.
- Current Assignee: MATERIALS ANALYSIS TECHNOLOGY INC.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06T7/60
- IPC: G06T7/60 ; G06T7/00

Abstract:
An automatic calculation method for thickness calculation of a deposition layer in a Fin-type field-effect transistor (FinFET) is disclosed through mapping edge lines onto an Excel spreadsheet. The similar method is also applied to the thickness calculation of superlattice or multiple quantum well for a light emitting diode (LED). The edge lines are obtained and transformed from an electronic image taken by Transmission Electron Microscopy (TEM), Focus Ion Beam (FIB), Atomic Force Microscopy (AFM), or X-Ray Diffraction (XRD) of the device.
Public/Granted literature
- US20150228065A1 DIMENSION CALCULATION METHOD FOR A SEMICONDUCTOR DEVICE Public/Granted day:2015-08-13
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