Invention Grant
- Patent Title: Digital circuit arrangements for ambient noise-reduction
- Patent Title (中): 用于环境降噪的数字电路布置
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Application No.: US14142329Application Date: 2013-12-27
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Publication No.: US09558729B2Publication Date: 2017-01-31
- Inventor: Richard Clemow
- Applicant: Wolfson Microelectronics plc
- Applicant Address: US TX Austin
- Assignee: Cirrus Logic, Inc.
- Current Assignee: Cirrus Logic, Inc.
- Current Assignee Address: US TX Austin
- Agency: Blank Rome LLP
- Priority: GB0607338.1 20060412
- Main IPC: G10K11/16
- IPC: G10K11/16 ; H04R3/02 ; H04R1/10 ; G10K11/178

Abstract:
A digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible. The arrangement converts the analog signals into N-bit digital signals at sample rate f0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed forward applications.
Public/Granted literature
- US20140112492A1 DIGITAL CIRCUIT ARRANGEMENTS FOR AMBIENT NOISE-REDUCTION Public/Granted day:2014-04-24
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