Invention Grant
US09559669B1 Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit
有权
用于产生时钟信号的电路和方法，使得能够在集成电路中锁存数据
- Patent Title: Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit
- Patent Title (中): 用于产生时钟信号的电路和方法，使得能够在集成电路中锁存数据
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Application No.: US14728741Application Date: 2015-06-02
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Publication No.: US09559669B1Publication Date: 2017-01-31
- Inventor: Brian C. Gaide
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent John J. King
- Main IPC: H03K3/017
- IPC: H03K3/017
Abstract:
A circuit for generating clock signals enabling the latching of data is described. The circuit comprises a pulse generator coupled to receive an input clock signal at an input and to generate an output clock signal at an output; a latch circuit coupled to receive the output clock signal; and a pulse shaping circuit coupled to receive a feedback signal; wherein a pulse width of the output clock signal is determined by the feedback signal and the input signal coupled to the pulse generator. A method of generating clock signals enabling the latching of data is also described.
Information query
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