Invention Grant
US09559676B1 Output buffer apparatus for controlling rate of rising/falling edge of buffered signal
有权
用于控制缓冲信号上升/下降沿速率的输出缓冲装置
- Patent Title: Output buffer apparatus for controlling rate of rising/falling edge of buffered signal
- Patent Title (中): 用于控制缓冲信号上升/下降沿速率的输出缓冲装置
-
Application No.: US14993104Application Date: 2016-01-12
-
Publication No.: US09559676B1Publication Date: 2017-01-31
- Inventor: Ming-Yu Hsieh
- Applicant: VIA Technologies, Inc.
- Applicant Address: TW New Taipei
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW New Taipei
- Agency: Jianq Chyun IP Office
- Priority: TW104128578A 20150831
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K5/12 ; H03K17/687
Abstract:
An output buffer apparatus is provided. A clamp circuit outputs a clamp voltage through a transistor pair having a first configuration. A bias circuit outputs a bias voltage through a transistor pair having a second configuration. A rate control circuit for rising/falling edge buffers an input signal according to the clamp voltage and the bias voltage to generate a buffered signal.
Information query
