A simulation apparatus that performs parallel execution of multiple logical processes obtained by modeling a plurality of components included in a system to be simulated. The apparatus includes: (i) a condition generating unit configured to generate, on the basis of communication delays between the multiple logical processes, constraint conditions to be satisfied by initial time shifts given to the multiple logical processes and look-ahead times each to be permitted by a message sent from a logical process serving as a communication source to a logical process serving as a communication destination to permit look-ahead; and (ii) a solver unit configured to solve an optimization problem that satisfies the constraint conditions and minimizes overhead in communication of messages between the multiple logical processes, and obtain the initial time shifts of the multiple logical processes and the look-ahead times between the multiple logical processes.