Invention Grant
US09564196B2 Semiconductor memory device and data writing method using a checkerboard pattern utilizing existing data supply bit addresses
有权
半导体存储器件和使用现有数据提供位地址的棋盘图案的数据写入方法
- Patent Title: Semiconductor memory device and data writing method using a checkerboard pattern utilizing existing data supply bit addresses
- Patent Title (中): 半导体存储器件和使用现有数据提供位地址的棋盘图案的数据写入方法
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Application No.: US15003317Application Date: 2016-01-21
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Publication No.: US09564196B2Publication Date: 2017-02-07
- Inventor: Tomotsugu Goto
- Applicant: Seiko Instruments Inc.
- Applicant Address: JP Chiba
- Assignee: SII SEMICONDUCTOR CORPORATION
- Current Assignee: SII SEMICONDUCTOR CORPORATION
- Current Assignee Address: JP Chiba
- Agency: Brinks Gilson & Lione
- Priority: JP2015-015374 20150129
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C8/18 ; G11C16/34 ; G11C29/10 ; G11C29/20 ; G11C29/36 ; G11C8/10 ; G11C16/08 ; G11C29/18

Abstract:
To provide a semiconductor memory device capable of writing a checkerboard pattern for interference and investigation by three writings regardless of the magnitude of memory capacity by making a change of a simple circuit configuration free from the need of a data holding circuit and a voltage converting circuit large in circuit area in a memory array in which the order of arrangement of bits is reversedly arranged between data words adjacent in a row direction. A row decoder and a column decoder are respectively configured to enable operation switching to an all selection mode and an even/odd-based selection mode in addition to a single address selection mode of a memory array by a control signal from a control circuit.
Public/Granted literature
- US20160225416A1 SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD Public/Granted day:2016-08-04
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