A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.