Invention Grant
- Patent Title: Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
- Patent Title (中): 用于半导体器件的后端制造的反向自对准双重图案化工艺
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Application No.: US14026893Application Date: 2013-09-13
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Publication No.: US09564361B2Publication Date: 2017-02-07
- Inventor: Stanley Seungchul Song , Choh Fei Yeap , Zhongze Wang , John Jianhong Zhu
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Toler Law Group, PC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; G06F17/50 ; H01L23/522 ; H01L21/033 ; H01L21/311
Abstract:
In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.
Public/Granted literature
Information query
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