Forming a CMOS with dual strained channels

Invention Grant

US09564373B2 Forming a CMOS with dual strained channels 有权

Title translation: 形成具有双应变通道的CMOS

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Patent Title: Forming a CMOS with dual strained channels
Patent Title (中): 形成具有双应变通道的CMOS
Application No.: US14633657

Application Date: 2015-02-27
Publication No.: US09564373B2

Publication Date: 2017-02-07
Inventor: Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
Applicant: International Business Machines Corporation
Applicant Address: US NY Armonk
Assignee: International Business Machines Corporation
Current Assignee: International Business Machines Corporation
Current Assignee Address: US NY Armonk
Agent Reza Sarbakhsh
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/02 ; H01L21/033 ; H01L29/78

Forming a CMOS with dual strained channels

Abstract:

The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.

Abstract(Chinese):

本发明一般涉及一种半导体器件，更具体地，涉及在相同晶片上形成压应变层和拉伸应变层的结构和方法。可以在拉伸应变层附近形成下部外延层。可以在下部外延层的一部分上形成上部外延层。热氧化可以将上部外延层转化为上部氧化物层，并且热凝结可导致下部外延层的一部分变成压缩应变层。可以去除上部氧化物层和下部外延层的剩余部分，留下拉伸应变层和压缩应变层。

Public/Granted literature

US20160254196A1 FORMING A CMOS WITH DUAL STRAINED CHANNELS Public/Granted day:2016-09-01

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS