An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a tile through wire twisting or through via connections and wires in another metal layer. Wires that change tracks may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires compared to the signal transition in conventional interconnect circuitry. At the same time, sub-optimal wire stitching in a routing tile that connects a wire that ends in the next routing tile to a wire that starts in the routing tile, whereby the two wires overlap each other may enable beneficial crosstalk, which may further improve signal transition time.