Invention Grant
- Patent Title: Semiconductor package and method of manufacturing the same
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US14369781Application Date: 2012-12-28
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Publication No.: US09564411B2Publication Date: 2017-02-07
- Inventor: Yun-Mook Park , Byoung-Yool Jeon
- Applicant: NEPES CO., LTD.
- Applicant Address: KR
- Assignee: NEPES CO., LTD
- Current Assignee: NEPES CO., LTD
- Current Assignee Address: KR
- Priority: KR10-2011-0145518 20111229
- International Application: PCT/KR2012/011767 WO 20121228
- International Announcement: WO2013/100709 WO 20130704
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/00 ; H01L23/31 ; H01L21/56 ; H01L25/03 ; H01L25/00 ; H01L23/498 ; H01L21/48 ; H01L23/538 ; H01L25/065

Abstract:
Disclosed herein is a semiconductor package having a fan-out structure in which a semiconductor chip is buried by an encapsulation member and an external connection member is disposed below the buried semiconductor chip. The semiconductor package includes an embedded rewiring pattern layer, an upper semiconductor chip disposed above the embedded rewiring pattern layer, an upper encapsulation member encapsulating the upper semiconductor chip, a lower semiconductor chip disposed below the embedded rewiring pattern layer, and a lower encapsulation member encapsulating the lower semiconductor chip to prevent exposure thereof.
Public/Granted literature
- US20140353823A1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2014-12-04
Information query
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