Invention Grant
- Patent Title: Three dimensional device integration method and integrated device
- Patent Title (中): 三维设备集成方法和集成设备
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Application No.: US14746425Application Date: 2015-06-22
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Publication No.: US09564414B2Publication Date: 2017-02-07
- Inventor: Paul M. Enquist , Gaius Gillman Fountain, Jr.
- Applicant: ZIPTRONIX, INC.
- Applicant Address: US CA San Jose
- Assignee: ZIPTRONIX, INC.
- Current Assignee: ZIPTRONIX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H01L21/58
- IPC: H01L21/58 ; H01L21/304 ; H01L23/00 ; H01L21/20 ; H01L21/683 ; H01L21/768 ; H01L21/822 ; H01L23/13 ; H01L23/36 ; H01L23/48 ; H01L23/538 ; H01L25/065 ; H01L25/16 ; H01L25/00 ; H01L27/06 ; H01L21/762 ; H01L21/18 ; H01L23/552 ; H01L25/18 ; H01L27/146

Abstract:
A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.
Public/Granted literature
- US20150287692A1 THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE Public/Granted day:2015-10-08
Information query
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