A clock circuit configured to generate a falling edge independently of an input clock signal is disclosed. In one embodiment, a clock circuit includes an input circuit coupled to receive an input clock signal. A corresponding first clock signal is provided on a first clock node, while a second clock signal that is a delayed version of the first is provided on a second clock signal. The clock circuit may generate an output clock signal based on the first and second clock signals and a feedback signal received from a functional circuit coupled to receive the output clock signal. The rising edge of the output clock signal is generated dependent upon when the rising edge of the input clock signal is received. The falling edge of the output clock signal is generated by the clock circuit independently of when the falling edge of the input clock signal is received.