Invention Grant
- Patent Title: Methods and systems for clocking a physical layer interface
- Patent Title (中): 物理层接口时钟的方法和系统
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Application No.: US14066583Application Date: 2013-10-29
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Publication No.: US09564905B2Publication Date: 2017-02-07
- Inventor: Prasad Chalasani , Venkata N. S. N. Rao
- Applicant: Kool Chip, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: SOCTRONICS, INC.
- Current Assignee: SOCTRONICS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Venture Pacific Law, PC
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/04 ; G06F1/12 ; G06F1/14 ; H04L7/00 ; H03L7/00 ; H03K19/0175 ; G06F13/38 ; G06F1/08 ; H03L7/08 ; H03L7/093 ; G06F1/28 ; G06F1/10 ; H04L25/02 ; G06F1/06
Abstract:
A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
Public/Granted literature
- US20140314190A1 Methods and Systems for Clocking a Physical Layer Interface Public/Granted day:2014-10-23
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