A memory controller includes a clock scaler, a bus component and a level monitor. The clock scaler is configured to receive a first clock signal and configured to generate a second clock signal based on the first clock signal, first and second frequency control signals. A frequency of the second clock signal may increase based on the first frequency control signal and decrease based on the second frequency control signal. The bus component may operate based on the second clock signal and generate a level signal corresponding to a current operating state of the bus component. The level monitor may generate the first and second frequency control signals based on the level signal, a first threshold value, a second threshold value, a first reference time, and a second reference time.