Invention Grant
- Patent Title: Implementing out of order processor instruction issue queue
- Patent Title (中): 执行乱序处理器指令发出队列
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Application No.: US14306328Application Date: 2014-06-17
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Publication No.: US09569222B2Publication Date: 2017-02-14
- Inventor: Chen Guo , John Ho , Ziad Saliba , Arash Shokouhbakhsh , Cheng-Fu F. Tsai
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joan Pennington
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30
Abstract:
A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction issue queue and ages are assigned to the accepted queue entry instructions using a queue counter. The queue entry instructions are issued based upon resources being ready and ages of the instructions. Ages of the queue entry instructions and the queue counter are selectively decremented, responsive to issuing instructions.
Public/Granted literature
- US20150363205A1 IMPLEMENTING OUT OF ORDER PROCESSOR INSTRUCTION ISSUE QUEUE Public/Granted day:2015-12-17
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