Invention Grant
- Patent Title: Multiple gate length vertical field-effect-transistors
- Patent Title (中): 多栅极长度垂直场效应晶体管
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Application No.: US14961179Application Date: 2015-12-07
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Publication No.: US09570356B1Publication Date: 2017-02-14
- Inventor: Karthik Balakrishnan , Kangguo Cheng , Pouya Hashemi , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Gibbons Gutman Bongini Bianco PL
- Agent Thomas S. Grzesik
- Main IPC: H01L29/772
- IPC: H01L29/772 ; H01L27/085 ; H01L21/82 ; H01L21/8234 ; H01L29/66 ; H01L29/78 ; H01L29/417 ; H01L29/423 ; H01L27/088 ; H01L21/308 ; H01L21/283

Abstract:
Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.
Information query
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