Invention Grant
- Patent Title: Semiconductor packages and related manufacturing methods
- Patent Title (中): 半导体封装及相关制造方法
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Application No.: US14677863Application Date: 2015-04-02
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Publication No.: US09570381B2Publication Date: 2017-02-14
- Inventor: Chun-Ting Lu , Chun-Hung Lin , Yi-Ting Chen
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaosiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaosiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/49
- IPC: H01L23/49 ; H01L23/495 ; H01L23/31 ; H01L21/48 ; H01L21/56
Abstract:
Described herein are semiconductor packages having an insulating layer and the manufacturing methods thereof, wherein semiconductor packages include a die pad; a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion; a chip disposed on the die pad and electrically connected to the leads; a molding compound encapsulating the chip, the inner lead portions and the trace portion, where the outer lead portions and a first surface of the trace portion are exposed from the molding compound; and an insulating layer covering the first surface of the trace portion.
Public/Granted literature
- US20160293531A1 SEMICONDUCTOR PACKAGES AND RELATED MANUFACTURING METHODS Public/Granted day:2016-10-06
Information query
IPC分类:
