Invention Grant
- Patent Title: Method of forming a damascene interconnect on a barrier layer
- Patent Title (中): 在阻挡层上形成镶嵌互连的方法
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Application No.: US13217172Application Date: 2011-08-24
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Publication No.: US09570396B2Publication Date: 2017-02-14
- Inventor: Takayuki Enda
- Applicant: Takayuki Enda
- Applicant Address: US CA Santa Clara
- Assignee: MONTEREY RESEARCH, LLC
- Current Assignee: MONTEREY RESEARCH, LLC
- Current Assignee Address: US CA Santa Clara
- Agency: Kunzler Law Group, PC
- Priority: WOPCT/JP2005/012059 20050630
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/768
Abstract:
A semiconductor device includes a first metal layer provided above a semiconductor substrate, an interlayer insulating film provided above the first metal layer, a second metal layer that is provided in an opening formed in the interlayer insulating film and is in contact with an underlying layer, the second metal layer being connected to the first metal layer, and a first barrier layer that is provided between the second metal layer and the interlayer insulating film and has a different main composition from that of the underlying layer.
Public/Granted literature
- US20110306201A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2011-12-15
Information query
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