Invention Grant
US09570421B2 Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
有权
堆叠多个模具用于形成三维集成电路(3DIC)结构
- Patent Title: Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
- Patent Title (中): 堆叠多个模具用于形成三维集成电路(3DIC)结构
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Application No.: US14079736Application Date: 2013-11-14
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Publication No.: US09570421B2Publication Date: 2017-02-14
- Inventor: Chih-Wei Wu , Ying-Ching Shih , Szu-Wei Lu , Jing-Cheng Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/065 ; H01L25/00 ; H01L23/14 ; H01L23/498 ; H01L23/31 ; H01L23/00 ; H01L23/48

Abstract:
The embodiments described provide methods and structures for forming support structures between dies and substrate(s) of a three dimensional integrated circuit (3DIC) structures. Each support structure adheres to surfaces of two neighboring dies or die and substrate to relieve stress caused by bowing of the die(s) and/or substrate on the bonding structures formed between the dies or die and substrate. The cost of the support structures is much lower than other processes, such as thermal compression bonding, to reduce the effect of bowing of dies and substrates on 3DIC formation. The support structures improves yield of 3DIC structures.
Public/Granted literature
- US20150130072A1 STACKING OF MULTIPLE DIES FOR FORMING THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) STRUCTURE Public/Granted day:2015-05-14
Information query
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