Invention Grant
- Patent Title: 3D clock distribution circuits and methods
- Patent Title (中): 3D时钟分配电路和方法
-
Application No.: US14636224Application Date: 2015-03-03
-
Publication No.: US09571073B2Publication Date: 2017-02-14
- Inventor: Mu-Shan Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H01L25/00 ; H03K5/01 ; H03K5/06 ; H03L7/00 ; H03K5/00

Abstract:
An integrated circuit includes a clock source tier and at least two clock distribution tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit. Each of the at least two clock distribution tiers includes a clock distribution circuit. Each clock distribution circuit includes at least one pair of cross-coupled inverters.
Public/Granted literature
- US20150180456A1 3D CLOCK DISTRIBUTION CIRCUITS AND METHODS Public/Granted day:2015-06-25
Information query