Invention Grant
- Patent Title: Test system and device
- Patent Title (中): 测试系统和设备
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Application No.: US14315127Application Date: 2014-06-25
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Publication No.: US09575114B2Publication Date: 2017-02-21
- Inventor: Jen-Shou Hsu , Po-Hsun Wu
- Applicant: Elite Semiconductor Memory Technology Inc.
- Applicant Address: TW Hsinchu
- Assignee: Elite Semiconductor Memory Technology Inc.
- Current Assignee: Elite Semiconductor Memory Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Marquez IP Law Office, PLLC
- Agent Juan Carlos A. Marquez
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/28

Abstract:
An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing.
Public/Granted literature
- US20150019927A1 TEST SYSTEM AND DEVICE Public/Granted day:2015-01-15
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