In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the cores to control power consumption of the processor. In turn, the PCU includes a control logic to cause the processor to re-enter a first package low power state responsive to expiration of an inter-arrival timer, where this expiration indicates that a time duration subsequent to a transaction received in the processor has occurred. Other embodiments are described and claimed.