Invention Grant
US09575761B2 System and method for updating an instruction cache following a branch instruction in a semiconductor device
有权
用于在半导体器件中的分支指令之后更新指令高速缓存的系统和方法
- Patent Title: System and method for updating an instruction cache following a branch instruction in a semiconductor device
- Patent Title (中): 用于在半导体器件中的分支指令之后更新指令高速缓存的系统和方法
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Application No.: US14223441Application Date: 2014-03-24
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Publication No.: US09575761B2Publication Date: 2017-02-21
- Inventor: Isao Kotera
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Womble Carlyle
- Priority: JP2013-069891 20130328
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F12/08 ; G06F12/12

Abstract:
A semiconductor device includes a memory for storing a plurality of instructions therein, an instruction queue which temporarily stores the instructions fetched from the memory therein, a central processing unit which executes the instruction supplied from the instruction queue, an instruction cache which stores therein the instructions executed in the past by the central processing unit, and a control circuit which controls fetching of each instruction. When the central processing unit executes a branch instruction, and an instruction of a branch destination is being in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes the instruction queue to fetch the instruction of the branch destination from the instruction cache and causes the instruction queue not to fetch the instruction following the instruction of the branch destination.
Public/Granted literature
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