An information processing apparatus includes: a plurality of memories; a plurality of buses each connected to each of the memories; an input/output device configured to make access to the plurality of memories; a processing unit configured to alter a mapping of a logical address and a physical address of a memory area used by the input/output device; and a switch configured to transfer access from the input/output device to any one of the plurality of buses based on the mapping, whereby the performance deterioration due to bus conflict is suppressed.