Invention Grant
US09576630B2 Memory devices and methods having multiple address accesses in same cycle
有权
在相同周期内具有多个地址访问的存储器件和方法
- Patent Title: Memory devices and methods having multiple address accesses in same cycle
- Patent Title (中): 在相同周期内具有多个地址访问的存储器件和方法
-
Application No.: US13179307Application Date: 2011-07-08
-
Publication No.: US09576630B2Publication Date: 2017-02-21
- Inventor: Dinesh Maheshwari
- Applicant: Dinesh Maheshwari
- Applicant Address: US CA San Jose
- Assignee: CYPRESS SEMICONDUCTOR CORPORATION
- Current Assignee: CYPRESS SEMICONDUCTOR CORPORATION
- Current Assignee Address: US CA San Jose
- Main IPC: G11C8/18
- IPC: G11C8/18 ; G11C8/16
Abstract:
A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.
Public/Granted literature
- US20120008378A1 MEMORY DEVICES AND METHODS HAVING MULTIPLE ADDRESS ACCESSES IN SAME CYCLE Public/Granted day:2012-01-12
Information query
