Invention Grant
US09576814B2 Method of spacer patterning to form a target integrated circuit pattern
有权
间隔物图案化以形成目标集成电路图案的方法
- Patent Title: Method of spacer patterning to form a target integrated circuit pattern
- Patent Title (中): 间隔物图案化以形成目标集成电路图案的方法
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Application No.: US14853857Application Date: 2015-09-14
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Publication No.: US09576814B2Publication Date: 2017-02-21
- Inventor: Chieh-Han Wu , Cheng-Hsiung Tsai , Chung-Ju Lee , Ming-Feng Shieh , Ru-Gun Liu , Shau-Lin Shue , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L21/02 ; H01L21/033 ; H01L21/027 ; H01L21/306 ; H01L21/311 ; H01L21/768
Abstract:
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.
Public/Granted literature
- US20160005617A1 METHOD FOR INTEGRATED CIRCUIT PATTERNING Public/Granted day:2016-01-07
Information query
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