Invention Grant
- Patent Title: Conductive paths through dielectric with a high aspect ratio for semiconductor devices
- Patent Title (中): 半导体器件具有高纵横比的介电导体通路
-
Application No.: US14717169Application Date: 2015-05-20
-
Publication No.: US09576918B2Publication Date: 2017-02-21
- Inventor: Thorsten Meyer , Andreas Wolter
- Applicant: INTEL IP CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL IP CORPORATION
- Current Assignee: INTEL IP CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/00 ; H01L21/78 ; H01L21/683 ; H01L21/56 ; H01L23/498 ; H01L23/522
Abstract:
Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a plurality of conductive connection pads are formed on a semiconductor substrate to connect to circuitry formed on the substrate. A post is formed on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is formed over the semiconductor substrate including over the connection pads and the posts. Holes are formed by removing the dielectric layer directly over the posts. The formed holes are filled with a conductive material and a connector is formed over each filled hole.
Public/Granted literature
- US20160343677A1 CONDUCTIVE PATHS THROUGH DIELECTRIC WITH A HIGH ASPECT RATIO FOR SEMICONDUCTOR DEVICES Public/Granted day:2016-11-24
Information query
IPC分类:
