Invention Grant
US09577038B1 Structure and method to minimize junction capacitance in nano sheets
有权
结构和方法使纳米片中的结电容最小化
- Patent Title: Structure and method to minimize junction capacitance in nano sheets
- Patent Title (中): 结构和方法使纳米片中的结电容最小化
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Application No.: US14969170Application Date: 2015-12-15
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Publication No.: US09577038B1Publication Date: 2017-02-21
- Inventor: Bruce B. Doris , Terence B. Hook , Xin Miao
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/336 ; H01L21/84 ; H01L29/66 ; H01L29/06 ; H01L21/02
Abstract:
A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the nanosheet stack; forming a first spacer along a sidewall of the gate stack; removing an endwall portion of the nanosheet stack that extends beyond the first spacer such that a portion of the second layer is exposed from a sidewall of the first spacer; depositing a second spacer along a sidewall of the first spacer; recessing the substrate beneath the second spacer to form an isolation region; depositing an oxide on the gate stack and within the isolation region and partially recessing the oxide; removing a portion of the second spacer such that the portion of the second layer is exposed; and growing an epitaxial layer on the portion of the second layer that is exposed to form a source/drain over the isolation region.
Information query
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