Invention Grant
- Patent Title: Transistor structure with reduced parasitic side wall characteristics
- Patent Title (中): 具有降低寄生侧壁特性的晶体管结构
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Application No.: US14585211Application Date: 2014-12-30
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Publication No.: US09577039B2Publication Date: 2017-02-21
- Inventor: Hubert Rothleitner
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: INFINEON TECHNOLOGIES AG
- Current Assignee: INFINEON TECHNOLOGIES AG
- Current Assignee Address: DE Neubiberg
- Agency: Viering, Jentschura & Partner MBB
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/423 ; H01L29/78 ; H01L29/49 ; H01L29/66 ; H01L29/10

Abstract:
A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).
Public/Granted literature
- US20160190248A1 TRANSISTOR STRUCTURE WITH REDUCED PARASITIC SIDE WALL CHARACTERISTICS Public/Granted day:2016-06-30
Information query
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