Invention Grant
US09577055B2 Semiconductor device having a minimized region of sheild electrode and gate electrode overlap
有权
具有最小化的电极和栅电极的区域的半导体器件重叠
- Patent Title: Semiconductor device having a minimized region of sheild electrode and gate electrode overlap
- Patent Title (中): 具有最小化的电极和栅电极的区域的半导体器件重叠
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Application No.: US14494858Application Date: 2014-09-24
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Publication No.: US09577055B2Publication Date: 2017-02-21
- Inventor: Jin Woo Han
- Applicant: Magnachip Semiconductor, Ltd.
- Applicant Address: KR Cheongju-si
- Assignee: Magnachip Semiconductor, Ltd.
- Current Assignee: Magnachip Semiconductor, Ltd.
- Current Assignee Address: KR Cheongju-si
- Priority: KR10-2013-0128705 20131028
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/40 ; H01L29/78 ; H01L29/06

Abstract:
The present disclosure relates to a semiconductor device. Such a semiconductor device includes a trench metal-oxide-semiconductor (MOS) transistor having two or more electrodes in a trench formed on a substrate of the semiconductor, where a part of a shield electrode positioned at a bottom of the trench is formed to have a large thickness, and a groove is formed in a gate electrode that is stacked on the shield electrode, such that a part of the shield electrode protrudes to a surface of the semiconductor device so as to be connected with a source power.In such a manner, by minimizing a region in which the shield electrode and the gate electrode overlap, a region that decreases problematic effects, such as leakage current of gate/source or gate/drain of a trench MOS transistor, and a region where high difference of a gate electrode is generated, are removed.
Public/Granted literature
- US20150115352A1 SEMICONDUCTOR DEVICE Public/Granted day:2015-04-30
Information query
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