Invention Grant
- Patent Title: Clock-gating cell with low area, low power, and low setup time
- Patent Title (中): 时钟门控单元,面积小,功耗低,安装时间低
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Application No.: US14598182Application Date: 2015-01-15
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Publication No.: US09577635B2Publication Date: 2017-02-21
- Inventor: Seid Hadi Rasouli , Steven James Dillen , Animesh Datta
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox LLP
- Main IPC: H03K17/687
- IPC: H03K17/687 ; H03K17/60 ; H03K19/00

Abstract:
A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.
Public/Granted literature
- US20160211846A1 CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME Public/Granted day:2016-07-21
Information query
IPC分类: